RCHD-PF - Using JTAG

Table of contents:

1 Windows guide
2 Prerequisites
3 Starting the OpenOCD server
4 GNU Debugger
5 Connecting GDB with OpenOCD:
6 Usufull GDB commands:
- 6.1 examine
- 6.2 set
- 6.3 restore

Windows guide

Prerequisites

FlashPro6 programmer from Microchip
Windows with WSL
Microchip SoftConsole v6.5
- <SoftConsolePath> will be required. Note it down on installation.
  For Windows WSL, the default path is /mnt/c/Microchip/SoftConsole-v6.5/

Starting the OpenOCD server

First we need to start the OpenOCD server. That will enable communication with PolarFireSoC's Risc-V cores via the FlashPro6 programmer:

Open a new user session in terminal
Run <SoftConsolePath>/openocd/bin/openocd -c "set DEVICE MPFS" --file board/microsemi-riscv.cfg
Expected output below. OpenOCD will log into this session when new events appear.

user@device:~$ /mnt/c/Microchip/SoftConsole-v6.5/openocd/bin/openocd.exe -c "set DEVICE MPFS" --file board/microsemi-riscv.cfg
xPack OpenOCD (Microchip SoftConsole build), x86_64 Open On-Chip Debugger 0.10.0+dev-00859-g95a8cd9b5-dirty (2020
-10-19-17:30)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html 
MPFS
Info : only one transport option; autoselect 'jtag'
Info : Hardware thread awareness created
do_board_reset_init
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : No Embedded FlashPro6 (revision B) devices found
fpServer v17 waiting for incoming connections on the port 3334 with API v5
Info : 1 1614681740419 microsemi_flashpro_server.c:1751 microsemi_flashpro_initialize() FlashPro ports available:
 138018D
Info : 2 1614681740419 microsemi_flashpro_server.c:1752 microsemi_flashpro_initialize() FlashPro port selected:
 138018D
Info : clock speed 6000 kHz
Info : JTAG tap: mpfs.cpu tap/device found: 0x0f81a1cf (mfg: 0x0e7 (GateField), part: 0xf81a, ver: 0x0)
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Core 0 could not be made part of halt group 1.
Info : Examined RISC-V core; found 5 harts
Info :  hart 0: XLEN=64, misa=0x8000000000101105
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Core 1 could not be made part of halt group 1.
Info : Examined RISC-V core; found 5 harts
Info :  hart 0: currently disabled
Info :  hart 1: XLEN=64, misa=0x800000000014112d
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Core 2 could not be made part of halt group 1.
Info : Examined RISC-V core; found 5 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: XLEN=64, misa=0x800000000014112d
Info :  hart 3: currently disabled
Info :  hart 4: currently disabled
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Core 3 could not be made part of halt group 1.
Info : Examined RISC-V core; found 5 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: XLEN=64, misa=0x800000000014112d
Info :  hart 4: currently disabled
Info : datacount=2 progbufsize=16
Info : Disabling abstract command reads from CSRs.
Info : Core 4 could not be made part of halt group 1.
Info : Examined RISC-V core; found 5 harts
Info :  hart 0: currently disabled
Info :  hart 1: currently disabled
Info :  hart 2: currently disabled
Info :  hart 3: currently disabled
Info :  hart 4: XLEN=64, misa=0x800000000014112d
Info : Listening on port 3333 for gdb connections

GNU Debugger

To run GDB:

Open a new user session terminal
Run the following multi-line single command
<SoftConsolePath>/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb \ -ex "set mem inaccessible-by-default off" \ -ex "set $target_riscv=1" \ -ex "set arch riscv:rv64"
Expected output:

user@device:~$ /mnt/c/Microchip/SoftConsole-v6.5/riscv-unknown-elf-gcc/bin/riscv64-unknown-elf-gdb.exe -ex "set mem inaccessible-by-default off" -ex "set $target_riscv=1" -ex "set arch riscv:rv64"
C:\Microchip\SoftConsole-v6.5\riscv-unknown-elf-gcc\bin\riscv64-unknown-elf-gdb.exe: warning: Couldn't determine
a path for the index cache directory.
GNU gdb (xPack GNU RISC-V Embedded GCC (Microsemi SoftConsole build), 64-bit) 9.1
Copyright (C) 2020 Free Software Foundation, Inc.
License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html >
This is free software: you are free to change and redistribute it.
There is NO WARRANTY, to the extent permitted by law.
Type "show copying" and "show warranty" for details.
This GDB was configured as "--host=x86_64-w64-mingw32 --target=riscv64-unknown-elf".
Type "show configuration" for configuration details.
For bug reporting instructions, please see:
<https://github.com/sifive/freedom-tools/issues >.
Find the GDB manual and other documentation resources online at:
    <http://www.gnu.org/software/gdb/documentation/ >.

For help, type "help".
Type "apropos word" to search for commands related to "word".
A syntax error in expression, near `=1'.
The target architecture is assumed to be riscv:rv64
(gdb)

Connecting GDB with OpenOCD:

To start debugging the RISC-V cores you have to first connect to the remote target. At the GDB console run: target remote localhost:3333

OpenOCD console should report the following:

Usufull GDB commands:

examine

examine / x reads memory content. Example:

set

set writes memory content. Example:

restore

restore writes memory content with data from file. Example:

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